[sv-ac] RE: Your note to mantis 3037

It should be noted that the proposal for 696 implements parameterized functions as static methods inside class definitions.

Regards,
Shalom

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Rich, Dave
Sent: Tuesday, January 18, 2011 11:21 PM
To: Korchemny, Dmitry; sv-ac@eda.org
Subject: [sv-ac] RE: Your note to mantis 3037

Parameterized functions (mantis 696<http://www.eda-stds.org/mantis/view.php?id=696>) are likely to pass in this rev of the standard.

But in any case, you did not explain why these functions need to be called "assertion" function.

There is only one logic "OR" operator in SystemVerilog, "|". There are restrictions on the operands to that operator based on the context of where the expression is located. However, those restrictions are described where the contexts are described, not with the operator. (Except for a possible cross-references)

Likewise, these functions should be described first as pure Boolean functions, then you can the restrictions or special contexts that assertions require.

Dave
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