[sv-ac] RE: Your note to mantis 3037

Parameterized functions (mantis 696
<http://www.eda-stds.org/mantis/view.php?id=696> ) are likely to pass in
this rev of the standard.

But in any case, you did not explain why these functions need to be
called "assertion" function.

There is only one logic "OR" operator in SystemVerilog, "|". There are
restrictions on the operands to that operator based on the context of
where the expression is located. However, those restrictions are
described where the contexts are described, not with the operator.
(Except for a possible cross-references)

Likewise, these functions should be described first as pure Boolean
functions, then you can the restrictions or special contexts that
assertions require.

Dave

From: Korchemny, Dmitry [mailto:dmitry.korchemny@intel.com]
Sent: Tuesday, January 18, 2011 4:50 AM
To: Rich, Dave; sv-ac@eda.org
Subject: Your note to mantis 3037

Hi Dave,

Addressing your note to mantis 3037:

-BEGIN-

These kinds of functional are also valuable for constraints and
coverage. Please do not label them 'assertion functions'

The list of these functions could grow enormously. Consider creating a
standard package of mathematical functions to perform these functions.
There is the problem that SV does not allow parameterized functions;
that may need to be addressed first.

-END-

Yes, this stuff does not have to reside in Clause 16 and be called
"Assertion system functions". We can place it in Clause 20 under" array
query functions" or add a different section "bit vector functions"
there. There is little hope that parameterized functions will be
introduced in this PAR. However, when they are introduced, it will be
possible to move these bit vector functions into a standard package.

Thanks,

Dmitry

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