[sv-ac] RE: continuous assignment example

Hi Manisha,

Please, see my comments below.

Thanks,
Dmitry

-----Original Message-----
From: Kulshrestha, Manisha [mailto:Manisha_Kulshrestha@mentor.com]
Sent: Tuesday, December 07, 2010 8:23 PM
To: Korchemny, Dmitry; sv-ac@eda.org
Subject: continuous assignment example

Hi Dimitry,

Here is the example we were discussing at the end of today's meeting:

randomization modifies the sampled value
continuous assignment modifies the sampled value
NBA does not modify the sampled value

checker c(a);
rand bit v;
bit x;
bit w;
always @clk x <= a;

assume property (@(clk) a == v);

assign w = $sampled(v & x) = v & $sampled(x);

assert property (@clk a == w);
assert property (@clk a == v);

endchecker

Just a followup on this example: when does the sampled value of x changes ?
[Korchemny, Dmitry] It changes in the Preponed region of the next time step, as regular design variables (since the LRM does not define where the sampled values change, it would be safer to say that in the Preponed region of the next tick the sampled value of x have a new value if a has changed).

If it changes in Preponed region of next time step, then will this continuous assignment evaluate again at next simulation tick ?
[Korchemny, Dmitry] According to the definition of continuous assignment it should.

But perhaps there is no need to do that as value of 'w' will not be used till next clock event.
[Korchemny, Dmitry] Indeed, there is no need to do that till the next clock event in this case. This is also the case unless the continuously assigned variables are used in a deferred assertion.

So, these continuous assignments are more like blocking assignments which happen between freevar update and assertion evaluation. Is that correct ?
[Korchemny, Dmitry] See my previous comment.

Manisha

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