RE: [sv-ac] automatic variiables in clock expr // virtual interface

hi Ben,

isn't the whole example illegal?

class test_class;
virtual test_if tf;
task run_c();
 expect ( @(posedge clk) tf.a |-> ##2 !tf.a); // <-- ******
endtask

tf is a dynamically assignable variable.

ed

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of ben cohen
Sent: Monday, June 14, 2010 9:17 AM
To: sv-ac@eda.org
Subject: [sv-ac] automatic variiables in clock expr // virtual interface

See http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=18142#18142
Lrm reference ?
Question is somewhat related to our upcoming discussion in interfaces and checkers.
Ben

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