RE: [sv-ac] automatic variiables in clock expr // virtual interface

<forwarding email from Daniel Mlynek>

-------- Original Message --------
From: "Daniel Mlynek" <danielm@aldec.com>
To: "'Bresticker, Shalom'" <shalom.bresticker@intel.com>,
         <ben@systemverilog.us>, <sv-ac@eda.org>
Subject: RE: [sv-ac] automatic variiables in clock expr // virtual interface
Date: Mon, 14 Jun 2010 15:42:05 +0200

Sensitivity list is also illegal. Could someone give an example for illegal
usage of virtual interface on sensitivity list, I see nothing wrong in
example:

interface ifc;
logic [7:0] data;
bit clk;
initial $monitor (data);
initial forever #5 clk =~ clk;
endinterface

module test;
  ifc Rx();
  virtual ifc vi=Rx ;
  byte data1;
  initial forever #5 data1++;
  //assign vi.data=data1; //illegal - ok
  always @vi.clk $display("event" ,$time); //legal???
  initial #101 $finish;
endmodule

DANiel

   _____

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Monday, June 14, 2010 3:25 PM
To: ben@systemverilog.us; sv-ac@eda.org
Subject: RE: [sv-ac] automatic variiables in clock expr // virtual interface

Maybe the following (25.9):

Once a virtual interface has been initialized, all the components of the
underlying interface instance are directly available to the virtual
interface via the dot notation. These components can only be used in
procedural statements; they cannot be used in continuous assignments or
sensitivity lists.

Shalom

   _____

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of ben
cohen
Sent: Monday, June 14, 2010 4:17 PM
To: sv-ac@eda.org
Subject: [sv-ac] automatic variiables in clock expr // virtual interface

See http://verificationguild.com/modules.php?name=Forums
<http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=18142
#18142> &file=viewtopic&p=18142#18142
Lrm reference ?
Question is somewhat related to our upcoming discussion in interfaces and
checkers.
Ben

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