RE: [sv-ac] Q: fix for rule (b) in 16.15.6 to allow inferred clock when expression appears in procedural assertion

Hi,

> > b) No term in expression1 appears anywhere else in the body of the
> > procedure, except in an assertion statement, expect
> statement, checker
> > or covergroup instantiation, or sampled value function.
> ----------
>
> Would it be reasonable to say that if we want to use these
> rules to auto-detect reset, this is OK, since a true reset
> would almost always be used directly rather than inside one
> of the constructs above?

You mean an asynchronous reset, of course.

> BTW-- I had one other thought about this whole discussion--
> while it came up in the context of assertions, this is really
> a more general aspect of the language, since we're discussing
> a rule change here for general procedures. Does this mean we
> have to move the issue to sv-bc rather than proposing a final
> resolution ourselves?

Is it more general today? Isn't this only for clock inference for assertions? Did SV-BC review this for 2009?

This is based on synthesis semantics, and in general, SV-BC prefers not to relate to simulation semantics.
It was done for assertions and some people were uncomfortable about it.
The preference is not to extend use of synthesis semantics more than necessary.

So I don't object to SV-BC reviewing this, but I believe they will not want to make this more general.

Regards,
Shalom
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