Re: [sv-ac] Contradictory statement of increment/decrement operators usage.

From: Surya Pratik Saha <spsaha_at_.....>
Date: Thu Aug 06 2009 - 06:54:44 PDT

Hi John,
I have filed Mantis 2839 for that.

Regards
Surya

-------- Original Message  --------
Subject: Re:[sv-ac] Contradictory statement of increment/decrement operators usage.
From: Havlicek John-R8AAAU <john.havlicek@freescale.com>
To: Surya Pratik Saha <spsaha@cal.interrasystems.com>
Cc: "sv-ac@server.eda.org" <sv-ac@eda.org>
Date: Thursday, August 06, 2009 5:09:15 PM

I am not aware of a mantis item for this -- please enter one.

 

J.H.

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From: Surya Pratik Saha [mailto:spsaha@cal.interrasystems.com]
Sent: Thursday, August 06, 2009 6:35 AM
To: Havlicek John-R8AAAU
Cc: sv-ac@server.eda.org
Subject: Re: [sv-ac] Contradictory statement of increment/decrement operators usage.

Hi,
Then I think LRM should have note in that section, otherwise people will get confused. Is there any Mantis against that, else I can file it.

Regards
Surya
  

-------- Original Message  --------
Subject: Re:[sv-ac] Contradictory statement of increment/decrement operators usage.
From: Havlicek John-R8AAAU <john.havlicek@freescale.com>
To: Surya Pratik Saha <spsaha@cal.interrasystems.com>, sv-ac@server.eda.org <sv-ac@eda.org>
Cc: "Havlicek John-R8AAAU" <john.havlicek@freescale.com>
Date: Thursday, August 06, 2009 5:02:05 PM

Hi Surya:

 

The intention is that for boolean expressions that are the building blocks of sequences, the operators with side effects are not allowed (as specified in 16.6.3).  However, for updating local variables in sequence match items, such operators may be used.  This could be clarified with an exception in 16.6.3 for sequence match items.

 

J.H.

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From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Surya Pratik Saha
Sent: Wednesday, August 05, 2009 11:43 PM
To: sv-ac@server.eda.org
Subject: [sv-ac] Contradictory statement of increment/decrement operators usage.

Hi,
In SV 2009 draft 7a LRM, it is mentioned:

16.6.3 Operators
All operators that are valid for the types described in 16.6.1 are allowed with the exception of assignment operators and increment and decrement operators. SystemVerilog includes the C assignment operators, such as +=, and the C increment and decrement operators, ++ and --. These operators cannot be used in expressions that appear in assertions. This restriction prevents side effects.

However, BNF of sequence_match_item shows following rules:
sequence_match_item ::=
operator_assignment
| inc_or_dec_expression
| subroutine_call

Are they not contradictory?

-- 
Regards
Surya
  

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