RE: [sv-ac] property instance in property expression

Hi Soumya,

Your code is correct provided the implementation of your properties and sequences is correct. Also, note that in your excerpt p2 is never defined, while p1 is defined twice.

Dmitry

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of soumya
Sent: Friday, December 19, 2008 12:54 PM
To: sv-ac@eda.org
Subject: [sv-ac] property instance in property expression

Hi,
 I have a quarry regarding usage of property instance in property expression.

Please consider the example.

property p1;
...........
endproperty

property p1;
.................
endproperty

sequence s1;
.............
endsequence

property prop;
@(posedge clk) s1 |-> ((prop1) or (prop2));
endproperty

One of the simulator giving error massage as :
"Illegal use of property name as a sequence or boolean expression."

Where as other simulator is simulating successfully.

I am confused here .

I noticed the BNF of property Expression

property_expr ::=
| property_expr or property_expr
| sequence_expr |-> property_expr
| property_instance

Please tell me what is the correct behavior.

Thanks,
-Soumya



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