[sv-ac] Editor question in Draft7 14.14

Hi Stu,

 

You put the following editor question at the beginning of 14.4:

 

"Is the term "entire elaborated SystemVerilog model" defined?"

 

The elaboration model is defined in 3.12 and 23.10.4, and it is
referenced in 20.10 as well. "Entire" is not a technical term here, but
an English adjective to emphasize that the whole elaboration model
should be considered.

 

Thanks,

Dmitry

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