RE: [sv-ac] 1987 verification statement -> assertion statement

I did not include "expect" in that class because it clearly did not fit
with the way assertion statement was used elsewhere. I think it is
clearly better than leaving it as is.

Lisa

-----Original Message-----
From: John Havlicek [mailto:john.havlicek@freescale.com] 
Sent: Wednesday, January 23, 2008 3:49 PM
To: Lisa Piper
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] 1987 verification statement -> assertion statement

Hi Lisa:

I like this approach.  The fact is that we have been using "assertion"
to mean asserts, assumes, and covers (and maybe also expects ...) for
a long time in phrases like "SystemVerilog Assertions".

The question about whether to include expects in this class remains,
and I am concerned that examining the status of expect with respect to
all things that will be conditioned by the phrase "assertion
statement" will not be feasible in the remaining time.

J.H.

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> Hi all,
> 
> Given the feedback from the champions that we should not be using
> "verification statement" because it is too broad, I decided to try to
> use "assertion statement".  We already use "assertion statement" in
many
> places in the text and it does not need to change. It seems to fit
well.
> I have not yet put this on Mantis. I would appreciate some feedback
> first.
> 
> Lisa
> 
> 
> 

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