RE: [sv-ac] ballot result for 1769

 Hello Shalom,

I have adjusted the text according to your 2 messages. Please see
attached text (and deposited on Mantis).

Regards,
ed

> -----Original Message-----
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
> Sent: Wednesday, January 23, 2008 12:00 AM
> To: Eduard Cerny
> Cc: sv-ac@eda.org
> Subject: RE: [sv-ac] ballot result for 1769
> 
> Also, the statement that "otherwise it will issue an 
> information message
> indicating which conditional branch was taken," is a little confusing.
> It sounds like only one message will be issued. Actually, N messages
> will be issued, one for the 0 branch, and N-1 for the non-zero branch.
> 
> Regards,
> Shalom
> 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.

attached mail follows:

This misuses the term 'scalar'. In Verilog, a 1-bit vector is not a
scalar, it is a 1-bit vector. A scalar in Verilog is by definition not a
vector. How about "if the vector is just 1 bit"?

Shalom


> > 3. "Elaboration messages are used to indicate if the vector 
> is just a
> > scalar,..."
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.