RE: [sv-ac] RE: 1698 sampled value functions - review

Hi,
 
There is a difference between the 9.2.2.4 text, which is informative
text that does not specify anything in the language definition in terms
of synthesis, and this text. The 9.2.2.4 is just a general statement
that the construct is useful for something. 
 
By the way, initial procedures are not normally synthesizable, so the
current text is not correct anyway.
 
Another inaccuracy in the text is "that meets the requirements for
modeling synthesizable sequential logic. Specifically, there can be one
and only one event control and no blocking timing controls."
As worded, that means that an always block with a blocking timing
control cannot be synthesized. That is simply not true.
 
What would be true is that if you write always and always_ff blocks
according to certain requirements, then they will be synthesizable.
However, you should not say that. It is possible to write an always_ff
procedure that is legal SV and is still not synthesizable.
 
Regards,
Shalom


________________________________

	From: Lisa Piper [mailto:piper@cadence.com] 
	Sent: Tuesday, January 22, 2008 11:35 PM
	To: Bresticker, Shalom; Eduard Cerny
	Cc: sv-ac@eda.org
	Subject: RE: [sv-ac] RE: 1698 sampled value functions - review
	
	

	Hi Shalom,

	 

	The one thing that remains, is as follows:

	 

	A clock can be inferred when placed in an always, always_ff or
initial procedure that meets the requirements for modeling synthesizable
sequential logic behavior. Specifically, there can be one and only one
event control and no blocking timing controls. If the event control
contains one and only one edge expression and its argument does not
appear anywhere else in the body of the procedure, then that edge
expression is the inferred clock.

	I used the same text as was already in 9.2.2.4

	9.2.2.4 Sequential logic always_ff procedure

	The SystemVerilog always_ff procedure can be used to model
synthesizable sequential logic behavior.

	For example:

	always_ff @(posedge clock iff reset == 0 or posedge reset) begin

	r1 <= reset ? 0 : r2 + 1;

	...

	Is this ok or should I rewrite it without a reference to
synthesis.  I have already deleted the other reference.

	 

	Lisa

	 

	
________________________________


	From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
	Sent: Tuesday, January 22, 2008 2:43 PM
	To: Eduard Cerny; Lisa Piper
	Cc: sv-ac@eda.org
	Subject: RE: [sv-ac] RE: 1698 sampled value functions - review

	 

	I agree with Ed's reservations about mention of synthesis
behavior. This came up in discussions of inferring reset signals, and it
was decided to word the requirements not in terms of synthesis.

	 

	Shalom

		 

		
________________________________


		From: owner-sv-ac@server.eda.org
[mailto:owner-sv-ac@server.eda.org] On Behalf Of Eduard Cerny
		Sent: Tuesday, January 22, 2008 9:30 PM
		To: Lisa Piper; Eduard Cerny
		Cc: sv-ac@server.eda.org
		Subject: [sv-ac] RE: 1698 sampled value functions -
review

		Hi Lisa, John,

		 

		I think that the proposal is ready  for  a vote. 

		 

		Still, I wonder about the following statement:

		 

		Since synthesized code executes in the active region,
the past_variable is used directly. Provided that

		the model follows synthesis rules and is race-free, the
behavior should be equivalent to that in the original

		model using $past. The other functions, $rose, $fell and
$stable follow.

		 

		Can we really talk about "synthesis rules" Which ones?
The LRM does not introduce it. Similarly in the restrictions on always
blocks, can we say 

		procedure that meets the requirements for modeling
synthesizable sequential logic behavior ?

		Finally, "default clock" should be perhaps changed to
"default clocking".

		 

		Best regards,

		ed

		 

			
________________________________


			From: Lisa Piper [mailto:piper@cadence.com] 
			Sent: Tuesday, January 22, 2008 10:22 AM
			To: Eduard Cerny
			Cc: sv-ac@eda.org
			Subject: 1698 sampled value functions

			<<1698_sampled_value_functions_08_1_22.pdf>> 

			Hi Ed,

			I have incorporated your suggestions.

			Lisa

		
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