[sv-ac] RE: Updated proposal for 1995 (concurrent assertions in loops) posted

Thanks Lisa-- I'll make the changes for #1 and #3.
 
For #2-- I think immediate assertions are inherently different from
concurrent ones.  Because they are less restricted & executed as part of
general procedural code, isn't it the case that we can have all sorts of
situations where the immediate assert would be attempted an arbitrary
number of times, possibly multiply or never for each iteration value?  I
think this should be addressed separately in 1729.

________________________________

From: Lisa Piper [mailto:piper@cadence.com] 
Sent: Friday, December 07, 2007 9:55 AM
To: Seligman, Erik; sv-ac@eda.org
Cc: Korchemny, Dmitry
Subject: RE: Updated proposal for 1995 (concurrent assertions in loops)
posted



Hi Erik,

 

Some more comments/questions:

 

"For a cover property statement that appears inside a procedural loop,
the measurement of "number of

times attempted" shall count each possible set of iterator values as one
attempt. Success or vacuous success

shall be measured and reported for each set of iterator values, as if
each were a separate attempt to execute the

coverage statement."

 

1.	I would say "cover" instead of "cover property" since there
exists "cover property" and "cover sequence", both of which are "cover".

2.	what happens if I put an immediate assertion in a loop?  Does
the attempt count need to be consistent with that of a concurrent
assertion in a loop? 
3.	This is not clear.  I suggest adding the word SET where shown:
"Success or vacuous success shall be measured and reported for each set
of iterator values, as if each set were a separate attempt to execute
the coverage statement." 

 

Lisa

________________________________

From: Seligman, Erik [mailto:erik.seligman@intel.com] 
Sent: Friday, December 07, 2007 12:12 PM
To: Lisa Piper; sv-ac@eda.org
Cc: Korchemny, Dmitry
Subject: Updated proposal for 1995 (concurrent assertions in loops)
posted

 

 

I added some comments in the coverage section, and a VPI change, in
response to Lisa's concerns.  

 

 

Erik Seligman

Formal Verification Architect

Corporate Design Solutions
Design Technology and Solutions

Intel Corporation

M.S. JF4-402                   
2111 NE 25th Ave
Hillsboro, OR 97124 

Phone:   (503) 712-3134

 


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