RE: [sv-ac] Draft4 review

Hello John,

I reviewed 1550 and 1674. Please see my comments below.

Best regards,
ed

------------

#1550  - no issues found.

#1674 -
- in the text

"The inferred enable condition is the expression defining the cumulative
condition required to reach the current
point within enclosing if-else and case blocks statements inside an
always or initial block procedure.
This is the same as the contextually inferred enabling condition for
verification statements (see 16.14.5). If
there are no enclosing if-else or case blocks statements, then the
cumulative condition is 1'b1 (true)."

should the if-else, case, always and initial be bold as keywords, as
indicated in the proposal?

- There is reference to default disable (1648), but this was not
approved at the time this change was implemented. The proposal for 1648
was updated following the most recent comments and should thus be voted
ASAP. 

- in
a4: assert property(p_multiclock(negedge clk2, ,posedge clk1, a, b, c,
d);

there should be a space after , as in

a4: assert property(p_multiclock(negedge clk2, , posedge clk1, a, b, c,
d);

- in 
 always @(posedge clk2 or posedge rst) begin
   if (rst) ... ;
   else if (d)
 end

perhaps it should be changed to

 always @(posedge clk2 or posedge rst) begin
   if (rst) ... ;
 end

because the "else if (d)" is just dangling there. This error is in the
proposal, but I think the correction should be made.

- in
"Assertion
a2 uses explicit reset value '0 in which case the disable iff statement
could be omitted altogether in the
equivalent assertion."

'0 should be changed to 1'b0.
(The same error is in the proposal.)

- in
"else block of the if (rst) statement and d is from the if block
statement and thus not negated."

should "else" be in bold as a keyword?

- Question: in several places we use the type bit as a cast function,
since bit is also a keyword, should it be bold in all its occurrences?
E.g., (!bit'(rst!=1'b0) && d)


-----------------------

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of John Havlicek
> Sent: Thursday, October 04, 2007 8:33 AM
> To: sv-ac@eda-stds.org
> Subject: [sv-ac] Draft4 review
> 
> Hi Folks:
> 
> We need to review the implementations in Draft4 of the 
> following Mantis
> items:
> 
> 1361 [TS/MK]
> 1460 [DK]
> 1550 [EC]
> 1674 [EC] (consider reference to 1648)
> 1677 [DK]
> 1704 [LP]
> 1730 [EC]
> 1734 [JH]
> 1735 [LP]
> 1768 [LP]
> 
> The owners of these items should review the implementation and send
> the results to the reflector.  Please consider any questions or issues
> in the notes from the Editor.
> 
> I would like for the reviews to be completed in one week (by
> 2007-10-11).  If the owner cannot do the review in this time, please
> try to find an alternate reviewer who can check the implementation in
> Draft4.
> 
> J.H.
> 
> 
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> 

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