RE: [sv-ac] {Filename?} imply and iff operators

Thanks Jonathan,

 I think that $ could be a problem because 

"P1 until$past(a)" could be hard to parse as well.

I am not very familiar with parsing. Does anybody who is familiar
with SV parsing can indicate whether the <until> make parsing harder? 

We have some discussions about the <> and everybody agree that they are
not esthetic. The reason that we didn't change them is that we could not
come with a better idea.

Doron

-----Original Message-----
From: Jonathan Bromley [mailto:jonathan.bromley@doulos.com] 
Sent: Monday, September 17, 2007 1:31 PM
To: Bustan, Doron; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] {Filename?} imply and iff operators

Doron,

Although it's not really my area of expertise, I am
very enthusiastic about your proposal to add LTL to
SVA, so I spent some time looking at your latest
version.  Please excuse me if I'm misunderstanding.

The strong operators <next> etc. are lexically very 
curious.  Since < and > are regular operators, I suspect
their existence as part of an LTL operator keyword may
make it very difficult for compilers to issue sensible
error diagnostics.  Given that $ is a legal character in
Verilog identifiers, would it not be preferable to use
"next$" instead?  Since $ already has an intuitive 
meaning of "infinity" in SVA, I think that would be
quite easy to read and remember.

Similarly, introducing a keyword-pair "until with" 
seems odd to me.  Personally I have no problem with
PSL's "until_", but I can see that it might be considered
hard to read.

I found a couple of very trivial typos:
- "week" for "weak"
- "ture" for "true"

Thanks for your efforts - I think LTL would be a great
addition to SVA.
--
Jonathan Bromley, Consultant

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