Doron, Although it's not really my area of expertise, I am very enthusiastic about your proposal to add LTL to SVA, so I spent some time looking at your latest version. Please excuse me if I'm misunderstanding. The strong operators <next> etc. are lexically very curious. Since < and > are regular operators, I suspect their existence as part of an LTL operator keyword may make it very difficult for compilers to issue sensible error diagnostics. Given that $ is a legal character in Verilog identifiers, would it not be preferable to use "next$" instead? Since $ already has an intuitive meaning of "infinity" in SVA, I think that would be quite easy to read and remember. Similarly, introducing a keyword-pair "until with" seems odd to me. Personally I have no problem with PSL's "until_", but I can see that it might be considered hard to read. I found a couple of very trivial typos: - "week" for "weak" - "ture" for "true" Thanks for your efforts - I think LTL would be a great addition to SVA. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Sep 17 21:51:27 2007
This archive was generated by hypermail 2.1.8 : Mon Sep 17 2007 - 21:52:16 PDT