RE: [sv-ac] immediate assertions in always_comb

Hi Jonathan,

I think that there is no problem with concurrent assertions in
always_comb blocks, at least in the current version of the LRM.
According to it the concurrent assertions in the always_comb blocks
shall be controlled by an explicitly specified clocking event (or
inferred from the default clocking). Therefore the procedure sensitivity
list does not affect the simulation of the concurrent assertion.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Jonathan Bromley
Sent: Tuesday, September 11, 2007 1:54 PM
To: Bustan, Doron; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] immediate assertions in always_comb

> I am not sure what "variable or select expression that is read" means.
> My interpretation was everything on the right hand side of an
> assignment.

It's definitely not restricted to that;  for example
the expression in an if() or case() test most certainly
must contribute to the block's sensitivity, as would
any expression supplied as an actual argument to a 
function.  I agree that "is read" in the LRM is not 
crystal-clear, which is why I generally re-phrase it 
as "participates in an expression".  I don't think
that distorts the meaning.

The problem gets *much* more interesting if you add
the ability to put concurrent assertions into 
always_comb.  Should the always_comb then be 
sensitised to the *sampled* (Preponed) values
of signals in the assertion?  Should it be 
sensitised to signals in the assertion at all?
Sorry, I haven't read that proposal yet, so
I don't know what has already been suggested
about this.
-- 
Jonathan Bromley, Consultant

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