> I am not sure what "variable or select expression that is read" means. > My interpretation was everything on the right hand side of an > assignment. It's definitely not restricted to that; for example the expression in an if() or case() test most certainly must contribute to the block's sensitivity, as would any expression supplied as an actual argument to a function. I agree that "is read" in the LRM is not crystal-clear, which is why I generally re-phrase it as "participates in an expression". I don't think that distorts the meaning. The problem gets *much* more interesting if you add the ability to put concurrent assertions into always_comb. Should the always_comb then be sensitised to the *sampled* (Preponed) values of signals in the assertion? Should it be sensitised to signals in the assertion at all? Sorry, I haven't read that proposal yet, so I don't know what has already been suggested about this. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Sep 11 03:56:51 2007
This archive was generated by hypermail 2.1.8 : Tue Sep 11 2007 - 03:57:06 PDT