RE: [sv-ac] immediate assertions in always_comb

Hi Doron,

 

I agree that 'c' should be part of sensitivity list in the equivalent
example. Jonathan as already pointed out the LRM section which makes it
clear.

 

Manisha

 

 

 

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Bustan, Doron
Sent: Tuesday, September 11, 2007 3:34 PM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] immediate assertions in always_comb

 

Hi,

 

I have a question regarding immediate assertions in always_comb

 

 For example

 

always_comb

begin

  a = b; 

  assert (a ==c)

end

 

is similar  to

 

always @(b) 

begin

  a = b;

  assert (a == c)

end

 

so if "c" is not equal to "a" at times where "b" does not change, it
does not fail the assertion.

This is a bit counter intuitive to me since always comb models wiring.
It would have been 

more intuitive if c was added to the sensitivity list as well.

 

Do other people share my intuition? Any problem with adding all signals
that are not

on the left hand side of an assignment to the sensitivity list?

 

Doron

 

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