> It seems reasonable to define a special term in the LRM specifying > the "whole thing", and then update 1681 proposal accordingly. We > believe that such basic terms should be introduced by SV-BC. VHDL calls it the "model". Since the word "design" has gained a colloquial meaning, as that part of the model that's executing in the "design regions" (Active/Inactive/NBA) of the scheduler, I agree with Dmitry that it would be a good idea to introduce a new term and use it consistently to describe the entire elaborated .... errrm .... model. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Aug 28 08:46:34 2007
This archive was generated by hypermail 2.1.8 : Tue Aug 28 2007 - 08:46:51 PDT