[sv-ac] 1691 Introduce global clocking

Hi all,

 

I had an action item to address the champions' comments concerning 1691
"Introduce global clocking". Please, find below my answer for your
review.

 

Thanks,

Dmitry

 

*	The proposal doesn't discuss what the global clock is with
respect to compilation units 

 

The global clocking is not directly related to the compilation units.
The requirement is to be at most one global clocking statement after the
elaboration stage.

 

*	There is no concept of globals in SystemVerilog 

 

The concept of globals is mentioned in the LRM. See for example Clause
3.12.3 "Simulation time unit". It states:

 

"The global time precision, also called the simulation time unit, is the
minimum of all the timeprecision statements and the smallest time
precision argument of all the `timescale compiler directives in the
design. The step time unit is equal to the global time precision."

 

There is also a notion of a global symbol/task/function in Clause 34.

 

*	It should be a tool option 

 

This seems to be problematic since a transition to a new tool becomes
unpredictable. We should take advantage of standardizing it, to make
this concept well-defined.

 

*	Strange that it is global and needs to be in a module, it should
be in compilation unit space 

 

Since the global clocking defines a clocking event, it makes sense to
consider it as a kind of clocking, and not as an absolutely new
construct. LRM defines that the clocking block shall not appear in a
compilation unit space, this is why the global clocking declaration
rules have been defined in a similar way. The consistency is crucial
here.

 

*	Not sure it fits in with the general usage of the language 

 

In the introduction to the LRM it is written:

"SystemVerilog enables the use of a unified language for abstract and
detailed specification of the design, specification of assertions,
coverage, and testbench verification that is based on manual or
automatic methodologies." 

 

This implies that SystemVerilog should answer the needs of
assertion-based formal verification. For formal verification of
synchronous systems the notion of the reference clock is important,
especially for multiclock design and for building abstract formal models
of the system. The detailed description of the motivation of this
feature may be found in the preamble to 1681.

 

Since formal verification of RTL is in scope of the language, the notion
of the reference clock needs to be covered by the language.

 

*	The LRM is based on event based simulation. 

 

This is exactly the reason why the global clocking is needed. There is
no need in a concept of global clocking for cycle-based simulation - the
notion of the reference clock is already in the language in this case.

 

*	If in a package would need to be imported 

 

Global clocking cannot be specified in a package.

 

*	Not sure why need this global thing, we already have clocking
blocks. 

 

Using clocking events defined by regular clocking blocks is not
different from the assertion point of view from the regular clocking
events. Using default clocking does not solve the problem, either,
because default clocking definition may differ from module to module. We
need to specify the same clock for all assertions that reference it
explicitly, to be able to explicitly specify a transition relation.

 

*	The proposal says that global clock is for the design. Can the
testbench use the global clock? (proposal seems to not say) 

 

Yes, the test bench is also part of the design. The global clocking just
defines an event which may be used everywhere. It does not differ from
any other event except for the formal semantics of assertions where it
is considered to represent the reference clock.

 

*	Proposal shouldn't use the term design if it isn't clear 

 

Unfortunately, there is no term in the LRM for the "whole thing" other
than design. The term "design" is already used in the LRM:

 

"The global time precision, also called the simulation time unit, is the
minimum of all the timeprecision statements and the smallest time
precision argument of all the `timescale compiler directives in the
design. The step time unit is equal to the global time precision."

 

(again citing 3.12.3).

 

It seems reasonable to define a special term in the LRM specifying the
"whole thing", and then update 1681 proposal accordingly. We believe
that such basic terms should be introduced by SV-BC.

 

 


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