RE: [sv-ac] Feedback on 1900 (new 'checker' construct)

Hi Brad,

I agree with you, the synthesizability aspect should not be mentioned in
the LRM. But introducing checkers allows a clear distinction for the
tools between RTL and the checker code. Therefore it is up to the tool
to decide whether to synthesize the checkers into silicon or not.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Brad Pierce
Sent: Wednesday, July 25, 2007 12:41 AM
To: sv-ac@server.eda-stds.org
Subject: Re: [sv-ac] Feedback on 1900 (new 'checker' construct)

>However, any construct within a checker should be defined as
non-synthesizable,
>and won't result in extra hardware in the design.

I don't think it's appropriate for this language standard to say
anything about what may or may not be synthesized.

Also, why wouldn't users want synthesized checkers in their
FPGA-accelerated test benches? 

[In reply to http://www.eda-stds.org/sv-ac/hm/4363.html .]

-- Brad


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