RE: [sv-ac] Updated proposal on 1674 (inferred_*) uploaded

Hi Dave,

Unfortunately the syntax rst = default cannot be adopted directly
because rst is an arbitrary formal argument of a property, and it may
have an arbitrary name, say, a; therefore it is not clear what default
value exactly is meant here (e.g., why not default clock?). rst =
disable does the work, in this case we should have clocking instead of
$inferred_clock, disable instead of $inferred_disable and something like
context instead of $inferred_enable. On the other hand $inferred_* names
are more intuitive since they reflect the intent directly. I don't think
that there is a danger that somebody redefines these functions since
they are handled at the elaboration time, and not at the simulation. We
have more examples like that in SystemVerilog already, e.g., function
$bits. 

The syntax rst = default.disable() is promising, but it requires
introducing a predefined object called default. Adopting this approach
poses several difficult questions: what is the class of this object?
What should be done when an object of this class is instantiated? etc.
It looks like this approach requires a serious revision of the whole
language.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Rich, Dave
Sent: Friday, May 25, 2007 10:11 PM
To: Seligman, Erik; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] Updated proposal on 1674 (inferred_*) uploaded

I still don't understand why this is a system function just some syntax
like

rst = default or rst = disable  or rst = default.disable()

In simulation, using $name for something means that it can be overridden
by the user through the PLI.

Something like default.disable() could be defined to be used in many
other contexts.

Dave


> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
On
> Behalf Of Seligman, Erik
> Sent: Friday, May 25, 2007 8:03 AM
> To: sv-ac@server.eda-stds.org
> Subject: [sv-ac] Updated proposal on 1674 (inferred_*) uploaded
> 
> 
> I have uploaded a modified proposal, with two major changes to address
> the recent objections:
> 
> - Added a motivation section, explaining why we are proposing this.
> - $inferred_* are now allowed only in default arguments, not arbitrary
> expressions.
> 
> 
> Those who voted NO last time-- pls take a look at
> http://www.verilog.org/mantis/bug_view_page.php?bug_id=0001674 & tell
us
> if these fixes sufficiently address your objections.  Thanks!
> 
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