RE: [sv-ac] Updated proposal on 1674 (inferred_*) uploaded

From: Rich, Dave <Dave_Rich_at_.....>
Date: Fri May 25 2007 - 12:11:23 PDT
I still don't understand why this is a system function just some syntax
like

rst = default or rst = disable  or rst = default.disable()

In simulation, using $name for something means that it can be overridden
by the user through the PLI.

Something like default.disable() could be defined to be used in many
other contexts.

Dave


> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
On
> Behalf Of Seligman, Erik
> Sent: Friday, May 25, 2007 8:03 AM
> To: sv-ac@server.eda-stds.org
> Subject: [sv-ac] Updated proposal on 1674 (inferred_*) uploaded
> 
> 
> I have uploaded a modified proposal, with two major changes to address
> the recent objections:
> 
> - Added a motivation section, explaining why we are proposing this.
> - $inferred_* are now allowed only in default arguments, not arbitrary
> expressions.
> 
> 
> Those who voted NO last time-- pls take a look at
> http://www.verilog.org/mantis/bug_view_page.php?bug_id=0001674 & tell
us
> if these fixes sufficiently address your objections.  Thanks!
> 
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Received on Fri May 25 12:11:46 2007

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