[sv-ac] question on $past

I have a question - The SV LRM IEEE-1800 section 17.7.3 says:

 

"If the specified clock tick in the past is before the start of
simulation, the returned value from the $past function is a value of X."

 

What about things that are not 4-state variables in SystemVerilog?  What
value should be returned?

 

Lisa


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