> > "The SystemVerilog always_ff procedure CAN be used to model > > synthesizable sequential logic behavior." > > > > It doesn't say always_ff SHALL be used for this purpose. True, but regular "always" can be, and is, used for modelling all manner of things for which clock, enable and disable inference would make absolutely no sense. always_ff fits the bill perfectly, costs almost nothing to users (there's no need to alter *any* good existing RTL code if you use it) and can only be used in situations where the clock/ena/disa inference is meaningful. It seems like a marriage made in heaven, to me. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Mar 12 02:14:06 2007
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