Re: [sv-ac] 1547 review

Hi Ed,

We shouldn't. I think the point is no need to put asserts in there as proposal.

THX. 
-Bassam

-----Original Message-----
From: Eduard Cerny <edcerny@synopsys.COM>
To: Rich, Dave <Dave_Rich@mentor.com>; john.havlicek@freescale.com <john.havlicek@freescale.com>
CC: Bassam.Tabbara@synopsys.COM <Bassam.Tabbara@synopsys.COM>; piper@cadence.com <piper@cadence.com>; sv-ac@eda-stds.org <sv-ac@eda-stds.org>
Sent: Wed Feb 21 11:37:51 2007
Subject: RE: [sv-ac] 1547 review

But the LRM already allows sequences and properties to be in cb. Can we
remove them now?
ed 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Rich, Dave
> Sent: Wednesday, February 21, 2007 2:34 PM
> To: john.havlicek@freescale.com
> Cc: Bassam.Tabbara@synopsys.COM; piper@cadence.com; sv-ac@eda-stds.org
> Subject: RE: [sv-ac] 1547 review
> 
> > 
> > It may be that there is no point in putting sequence or property
> > declarations in a clocking block, in which case this proposal
> > would be unnecessary.
> > 
> > J.H.
> > 
> [DR>] That was my point.
> 
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