Re: [sv-ac] reminder to vote on mantis 1550

Hi Shalom:

In any case, the first call to 

   execute_time_slot(T)

and therefore also the first call to 

   execute_region (preponed)

do not occur until after

   initialize the values of all nets and variables; 

This is the evidence that leads me to conclude that the 
values set in declaration assignments are visible in the 
preponed region of the time 0 slot.

J.H.

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> In fact, the first thing the simulation reference algorithm in 9.3.1
> does is to initialize T to 0.
> 
> Shalom
> 
> 
> > 6.4 says "In SystemVerilog, setting the initial value of a static
> > variable as part of the variable declaration (including static class
> > members) shall occur before any initial or always blocks are started."
> > 
> > There is no definition of "before time 0"
> 
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