Re: [sv-ac] bind statement

Ed,
Please consider this case, does this example support that line?

interface counter_IFC;
logic reset;
logic [3:0] out ;
endinterface : counter_IFC

module counter (counter_IFC count, input bit clk );
always @( posedge clk)
begin
if(count.reset == 1'b1)
count.out <= 0;
else
count.out <= count.out + 1;
end

I inst3 (.*);
endmodule

interface I (counter_IFC count, input bit clk);

sequence seq;
@(posedge clk)
count.out[0] ##1 (!count.out[0] && count.out[1]);
endsequence

property p1;
@(posedge clk)
count.reset ##1 !count.reset |=> seq ;
endproperty

bind counter I inst2(count, clk);

always @(posedge clk)
assert property(p1);

endinterface

Thanks & Regards
Soumya