FW: [sv-ac] FW: #805

Resend for Manisha

-----Original Message-----
From: owner-sv-ac@server.eda-stds.org
[mailto:owner-sv-ac@server.eda-stds.org] On Behalf Of Kulshrestha,
Manisha
Sent: Friday, June 16, 2006 7:51 PM
To: Lisa Piper; Eduard Cerny; Bassam Tabbara; Bassam Tabbara;
sv-ac@server.verilog.org
Subject: RE: [sv-ac] FW: #805

Hi All,

I think we need to look at some of the callbacks for assertions as
described below (page 471):

cbAssertionDisable, cbAssertionEnable, cbAssertionReset,
cbAssertionKill:

cb_time is the time when the assertion attempt was disabled, enabled,
reset, or killed.

Two of the callbacks which are of interest are cbAssertionDisable and
cbAssertionReset. Although LRM is not clear on these but looks like
cbAssertionDisable should apply to the disabling due to assertion system
control task $assertoff and vpi_control (vpiAssertionDisable ..). Where
as cbAssertionReset should apply to reset due to disable iff and
vpi_control(vpiAssertionReset ...) ?

cbAssertionEnable - enabling due to $asserton and
vpi_control(vpiAssertionEnable ...)
cbAssertionKill - killing due to $assertkill and
vpi_control(vpiAssertionKill...)

Now, cbAssertionReset is similar to what we are trying to define here
for disable iff condition. If not, is it possible to enhance its
definition to handle the disable iff case also ?

Manisha