RE: [sv-ac] Porposal for disable iff

Hi Adam,

We are going to come up with another proposal to help Verilog
programmers. We are planning to introduce new system tasks to
enable/disable execution of pass actions in case of different types of
successes. These tasks will work like assertion control system tasks. 

Thanks.
Manisha 

-----Original Message-----
From: Adam Krolnik [mailto:krolnik@lsil.com] 
Sent: Tuesday, February 07, 2006 9:25 AM
To: Kulshrestha, Manisha
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] Porposal for disable iff



Hi Manisha;

While this proposal helps the VPI writer, it does not remove the
ambiguity for the verilog programmer.
It would be good to resolve the ambiguity for the verilog programmer.

It would be good if the verilog programmer would be able to distinguish
the success of a property from the vacuous success or disabling of the
property so that they can use the pass and fail action statements
appropriately.

   Thank you.

-- 
    Adam Krolnik
    ZSP Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion-Based Design"