Re: [sv-ac] Porposal for disable iff

Hi Manisha;

While this proposal helps the VPI writer, it does not remove the 
ambiguity for the verilog programmer.
It would be good to resolve the ambiguity for the verilog programmer.

It would be good if the verilog programmer would be able to distinguish 
the success of a property from the
vacuous success or disabling of the property so that they can use the 
pass and fail action statements appropriately.

   Thank you.

-- 
    Adam Krolnik
    ZSP Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion-Based Design"