Re: [sv-ac] Semantics of "calling subroutines on match of a seque nce" is not well defined.

Ben,

thanks for your respond, I'm afraid I wasn't clear enough. I will try to
make my questions more clear.

At the  sequence

 sequence s1;
   ((a[*2] , $display("aa")) #1 a)
intersect
   b[*3];
 endsequence

I can see two different approaches

  1. Consider only the subsequence (a[*2] , $display("aa")). Since this 
subsequence
       matches the prefix of the computation, the $display should be 
executed after the second cycle.

   2. Consider the whole sequence. Since in the first cycle of the 
computation b is low,
        the sequence fails at cycle 1, and thus, the $display should not 
be executed.

At the sequence

 sequence s2;
( (a #1 a) or (b #1 b) ) #1  (c, $display("c"));
 endsequence

The question is not whether the $display should be executed after cycle 
3, but how many times:
once or twice. To make this more clear, consider the following sequence

sequence s3;
logic [2:0] v;

(
   ((a ##1 a), v=1)
or
   ((b ##1 b), v=2)
) ##1 (c, $display("c, v=%d", v));

endsequence

For a computation where a,b, and c are high in the first
3 cycles, I would expect 2 executions of the $display, one with
v = 1, and the other with v=2.

So in the case of s2 haw many times the $display should be execute 1 or 2?

Doron


vhdlcohen@aol.com wrote:

>  Doron,
>  My understanding is below:
>  sequence s1; ((a[*2] , $display("aa")) #1 a) intersect b[*3];
>  endsequence
>   At the the second "a", the endpoint of the sequence a[*2] and
> regardless of combinations of "aa",
>  the $display should be executed.
>
>   "In other cases it is not clear how many times a subroutine should be
> called
>  in a given cycle. For example in the sequence
>  sequence s2; ( (a #1 a) or (b #1 b) ) #1
>  (c, $display("c"));
>  endsequence
>  In case that a,b, and c are high at the first 3 cycles, it is not
>  clear how many times the $display should be executed. "
>
>   Same thing here, at then endpoint of "( (a #1 a) or (b #1 b) ) #1 ",
> when "c" is reached ,
>   and regardless of the value of "a" or "b", the $display should be
> executed.
>   In the above example, a user would want to put such subroutines in the
> consequent rather than the antecedent.
>
>  Any disagreement to my opinions?
>
>  
> -------------------------------------------------------------------------
> -
>  Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
>  http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org
>  * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
>   * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
> Edition, 2004, ISBN 0-9705394-6-0
>   * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
>  * Component Design by Example ", 2001 isbn 0-9705394-0-1
>   * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
> 0-7923-8474-1
>   * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
> 0-7923-8115
>  
> -------------------------------------------------------------------------
> --------
>
>  
>