RE: [sv-ac] Ballot item 241 proposal

Hi,

I wonder if the examples in Mantis #626 (issue 241) should also include the
following situation:

clocking ck @(posedge clk);
  input a;
endclocking

property p3;
  @ck ck.a;
endproperty

a5: assert property(p3);

This would be the case of possible double sampling too and it should state
again that the results is the same as in the other cases a1-a4. Or is this
illegal?

And an example of the illegal case:

clocking ck @(posedge clk);
  input #1 a;
endclocking

property illegal_sampling;
  @ck ck.a;
endproperty

a5: assert property(illegal_sampling);

-----------
And what about the following case? Is it legal? If we go by the timing
diagram in the proposal, this would mean resampling the sampled value by
posedge clk by the posedge of clk2:

clocking ck @(posedge clk);
  input a;
endclocking

property p4;
  @(posedge clk2) ck.a;
endproperty

a5: assert property(p4);

----------

ed



> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Surrendra Dudani
> Sent: Thursday, April 14, 2005 8:58 PM
> To: sv-ac@eda.org
> Subject: [sv-ac] Ballot item 241 proposal
> 
> 
> Please review ballot issue 241 with Manisha's proposal in 
> mantis item #626.
> If I don't hear anything by tomorrow, I'll assume it's ok to 
> change the
> status to resolve.
> Surrendra
> ****************************************
> Surrendra A. Dudani
> Synopsys, Inc.
> 377 Simarano Drive, Suite 300
> Marlboro, MA 01752
> 
> Tel:   508-263-8072
> Fax:   508-263-8123
> email: Surrendra.Dudani@synopsys.com  
> **************************************** 
> 
> 
>