Re: [sv-ac] AC 196:

Ed:

I have not looked through all the mail in my buffer, so I offer
my apologies for duplicating any answers.

I think the intended semantics of pass by value is that

   sequence foo(bit a, ref bit b); // a is passed by value
      (t == a)*[0:$] ##1 b
   endsequence
      
be equivalent to

   sequence foo(ref bit a, ref bit b);
      bit loc_a;
      (1'b1, loc_a = a) ##0
      (t == loc_a)*[0:$] ##1 b
   endsequence
      
and similarly. The signals in the support of an actual argument
passed to the formal value argument of an instance of foo will
be sampled in the preponed region in the timestep of activation
of the instance. However, as evaluation of the instance progresses
in time, there will not be any resampling of these signals. On the
other hand, signals in the support of the actual argument passed to
the formal reference argument of the instance will be resampled in
the preponed region of each timestep (at least at those for which
the clock event governing the instance is true).

Best regards,

John H.

>
> Hi Hillel,
>
> If I understand it right, then effectively passing by value would remove the
> sampling in preponed region (is it what we want?). But, as John also
> mentioned, I am not clear on when the values are taken from the variable
> passed through that kind of argument.
>
> ed
>
>
> > -----Original Message-----
> > From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> > Sent: Wednesday, November 17, 2004 6:13 AM
> > To: 'Adam Krolnik'
> > Cc: Eduard.Cerny@synopsys.COM; sv-ac@eda.org; Miller Hillel-R53776
> > Subject: RE: [sv-ac] AC 196:
> >
> > Adam,
> >
> > Your examples are correct.
> >
> > I prefer the form of a task because you have a definition of
> > 'pass by value' and 'pass by reference'. I believe that both
> > of these are needed. With modules I just have pass by
> > reference. The 'pass by value' saves the need of sampling and
> > then calling the sequence.
> >
> > Thanks
> > Hillel
> >
> > -----Original Message-----
> > From: Adam Krolnik [mailto:krolnik@lsil.com]
> > Sent: Tuesday, November 16, 2004 10:39 PM
> > To: Miller Hillel-R53776
> > Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
> > Subject: Re: [sv-ac] AC 196:
> >
> >
> >
> >
> > Hi Hillel, Eduard;
> >
> > So as a comparative set of properties, these are the
> > equivalent forms, correct?
> >
> >
> > property rule6_with_no_type(x, y);
> > ##1 x |-> ##[2:10] y;
> > endproperty
> >
> > property rule6_with_type(ref bit x, ref bit y);
> > ##1 x |-> ##[2:10] y;
> > endproperty
> >
> >
> > And these are definitely not the same...
> >
> > property rule6_with_no_type(x, y);
> > ##1 x |-> ##[2:10] y;
> > endproperty
> >
> > property rule6_wrong_type(bit x, bit y);
> > ##1 x |-> ##[2:10] y;
> > endproperty
> >
> >
> > I would have though the model was that of a module, not a
> > model of a task (call or
> > invocation.) With a model of a module, then ports would not
> > need the 'ref' keyword to be able to monitor the (possibly)
> > changing (in time) value of expressions.
> >
> >
> > Thanks.
> >
> > Adam Krolnik
> > Verification Mgr.
> > LSI Logic Corp.
> > Plano TX. 75074
> > Co-author "Assertion-Based Design"
> >
>
Received on Wed Nov 17 18:28:26 2004