RE: [sv-ac] AC 196:

Adam,

Your examples are correct.

I prefer the form of a task because you have a definition of 'pass by value' and 'pass by reference'. I believe
that both of these are needed. With modules I just have pass by reference. The 'pass by value' saves the
need of sampling and then calling the sequence.

Thanks
Hillel

-----Original Message-----
From: Adam Krolnik [mailto:krolnik@lsil.com]
Sent: Tuesday, November 16, 2004 10:39 PM
To: Miller Hillel-R53776
Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
Subject: Re: [sv-ac] AC 196:

Hi Hillel, Eduard;

So as a comparative set of properties, these are the equivalent forms, correct?

property rule6_with_no_type(x, y);
   ##1 x |-> ##[2:10] y;
endproperty

property rule6_with_type(ref bit x, ref bit y);
   ##1 x |-> ##[2:10] y;
endproperty

And these are definitely not the same...

property rule6_with_no_type(x, y);
   ##1 x |-> ##[2:10] y;
endproperty

property rule6_wrong_type(bit x, bit y);
   ##1 x |-> ##[2:10] y;
endproperty

I would have though the model was that of a module, not a model of a task (call or
invocation.) With a model of a module, then ports would not need the 'ref' keyword to
be able to monitor the (possibly) changing (in time) value of expressions.

     Thanks.

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"
Received on Wed Nov 17 03:12:56 2004