RE: [sv-ac] AC 196:

Bassam,

input/outputs would not be allowed in this proposal.
If a BNF allows something it does not mean that it is supported.
This could be reported as unsupported or semantically not defined by a tool.
The trade off would be to define a new BNF which I think would be much more expensive.
I would rather say what is not allowed semantically in the current tf_port_list BNF for sequences
and properties.

Thanks
Hillel

-----Original Message-----
From: Bassam Tabbara [mailto:bassam@novas.com]
Sent: Wednesday, November 17, 2004 12:05 AM
To: 'Adam Krolnik'; Miller Hillel-R53776
Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
Subject: RE: [sv-ac] AC 196:

Hi Adam,

The first 2 (i.e. ref vs. no ref) are not equivalent (first should have
"pass by value" semantics (regardless of how it's actually done)), so that
answers your last reflection there ...

Thx.
-Bassam.

P.S. Hillel, in addition to Ed's questions: What would the input/output/...
Mean ? We certainly only mean to have input there I think ... If we use
tf_port_list, we'll get all the rest too ...

--
Dr. Bassam Tabbara
Architect, R&D
Novas Software, Inc.
(408) 467-7893
-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Adam
Krolnik
Sent: Tuesday, November 16, 2004 12:39 PM
To: Miller Hillel-R53776
Cc: 'Eduard.Cerny@synopsys.com'; sv-ac@eda.org
Subject: Re: [sv-ac] AC 196:
Hi Hillel, Eduard;
So as a comparative set of properties, these are the equivalent forms,
correct?
property rule6_with_no_type(x, y);
   ##1 x |-> ##[2:10] y;
endproperty
property rule6_with_type(ref bit x, ref bit y);
   ##1 x |-> ##[2:10] y;
endproperty
And these are definitely not the same...
property rule6_with_no_type(x, y);
   ##1 x |-> ##[2:10] y;
endproperty
property rule6_wrong_type(bit x, bit y);
   ##1 x |-> ##[2:10] y;
endproperty
I would have though the model was that of a module, not a model of a task
(call or
invocation.) With a model of a module, then ports would not need the 'ref'
keyword to be able to monitor the (possibly) changing (in time) value of
expressions.
     Thanks.
     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"