[sv-ac] AC 196 - optional type spec?

Hello,

It seems to me that there may be a problem in allowing optional type
specification on formal arguments to sequences and properties for the
following reason:

If I understand the LRM correctly, a tf_port_list can be specified as
follows:

(a, type_spec1 x, y, type_spec2 v, w)

in this case a is of type wire (?), x AND y are of type type_spec1, v AND w
are of type type_spec2.

How does one distinguish omitted type from a type propagating from a
preceding declaration or be implicit?

Can we add a restriction such that untyped formals are specified first,
followed by typed formals? In that case a in the above example would be
untyped.

ed
Received on Fri Nov 12 15:04:36 2004