Re: [sv-ac] technical reports // variable as ranges

Hi Ben:

From the perspective of the formal semantics, local variables
cannot influence the endpoints of temporal ranges. This is
because all temporal range operators are defined as derived
from explicit constant range operators. In other words, the
endpoints of the temporal range operators must be compile-time
constants. I do not know if the BNF allows your example, but
there is no formal semantics defined for your use of local
variables in the endpoints of ##[m:n] and [*m:n]. Thus, I
would have to say that your example is illegal.

However, you can use a local variable in a boolean expression,
such as a comparison to another local variable. Therefore, you
could code something like the following to capture the same
(or, in case I have goofed, similar) intended meaning:

   sequence qReqAckDone(upper, lower, rep);

      int vupper, vlower, vrep, x;

      (req, vupper=upper, vlower=lower, vrep=rep, x = 0)
      ##1 (x < vupper, x = x+1)[*0:$]
      ##0 ((x >= vlower) && ack, x = 0)
      ##1 (xfr && (x < vrep), x = x+1)[*0:$]
      ##1 done;

   endsequence : qReqAckDone

Regarding descending temporal ranges, these are also not given
any formal semantics. Therefore, they should result in compile-time
errors.

A local variable can be used as a bit selector or as the base of a
variable part selector.

Best regards,

John H.

>
> With reference to Accellera Technical Report 2004.0, "Notes on the
> Semantics of Local Variables in Accellera SystemVerilog 3.1 Concurrent
> Assertions" you did not address whether a variable can be used to
> describe a range. I believe, from the LRM, that it is legal.
> For example,
>
> sequence qReqAckDone(upper, lower, rep);
>
> int vupper, vlower, vep;
>
> (req, vupper=upper, vlower=lower, vrep=rep)
>
> ##[vlower:vupper] ack ##1 xfr[*0:vrep] ##1 done;
>
> endsequence : qReqAckDone
>
> 1. I want to confirm that it is legal.
>
> 2. What happens if the range is a downward range, like [10: 3} or even
> a negative range, like [-3: 5], [-3: -10], [-10: -4]? Is that
> considered a "null" range a la VHDL?
>
> Or, is this totally illegal, and a runtime error would occur?
>
>
>
> Thanks,
>
> Ben
>
> ------------------------------------------------------------------------
> -----
> Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
> http://www. <http://www.vhdlcohen.com/> vhdlcohen.com/ vhdlcohen@aol.com
>
> Author of following textbooks:
> * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004
> isbn 0-9705394-6-0
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
> 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
> 0-7923-8115
> ------------------------------------------------------------------------
> ------
>
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Received on Tue, 29 Jun 2004 00:53:36 -0500 (CDT)