Re: [sv-ac] technical reports // variable as ranges

With reference to Accellera Technical Report 2004.0, "Notes on the Semantics
of Local Variables in Accellera SystemVerilog 3.1 Concurrent Assertions" you
did not address whether a variable can be used to describe a range. I
believe, from the LRM, that it is legal.
For example,
 
sequence qReqAckDone(upper, lower, rep);
int vupper, vlower, vep;
(req, vupper=upper, vlower=lower, vrep=rep)
##[vlower:vupper] ack ##1 xfr[*0:vrep] ##1 done;
endsequence : qReqAckDone
1. I want to confirm that it is legal.
2. What happens if the range is a downward range, like [10: 3} or even a
negative range, like [-3: 5], [-3: -10], [-10: -4]? Is that considered a
"null" range a la VHDL?
Or, is this totally illegal, and a runtime error would occur?
Thanks,
Ben
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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
_http://www.vhdlcohen.com/_ (http://www.vhdlcohen.com/) vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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Received on Mon Jun 28 20:20:32 2004