[sv-ac] SVA: bind_directive syntax not same as LRM 17.15 description

A.1.5 _bind_directive_
(file:///C:/sysvlog/psl_lab/pslbk_doc/SV3.1a_bnf_no_footnotes.htm#Rbind_directive) ::= bind _hierarchical_identifier_
(file:///C:/sysvlog/psl_lab/pslbk_doc/SV3.1a_bnf_no_footnotes.htm#hierarchical_identifier_
DEF_) _constant_select_
(file:///C:/sysvlog/psl_lab/pslbk_doc/SV3.1a_bnf_no_footnotes.htm#constant_select_DEF_) _bind_instantiation_
(file:///C:/sysvlog/psl_lab/pslbk_doc/SV3.1a_bnf_no_footnotes.htm#bind_instantiation_DEF_) ;
Meaning that only instantiations are allowed. Yet, LRM 17.15 is quite
clear in saying "properties can be bound to either modules or module instances"
at multiple places. The last example in that section shows:
 
bind cr_unit range r1(c_clk,c_en,v_low,(in1&&in2));

 
In this example, interface range is instantiated in the module cr_unit.
Effectively, every instance of module
cr_unit shall contain the interface instance r1.
The syntax for the directive needs to be change to reflect that module names
and interface names are also allowed, besides just instances.
Ben

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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
_http://www.vhdlcohen.com/_ (http://www.vhdlcohen.com/) vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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Received on Thu Jun 24 09:49:44 2004