[sv-ac] SVA: LRM 17.8 // Parentheses with sequence_match_item

LRM requires parentheses when sequence match item is used. Yet,
LRM document is not consistent with this requirement.
17.8 Manipulating data in a sequence
...
sequence_expr ::=
...
| ( expression_or_dist {, sequence_match_item } ) [ boolean_abbrev ]
| ( sequence_expr {, sequence_match_item} ) [ sequence_abbrev ]
...
a ##1 (b[->1], x = e) ##1 c[*2]
sequence data_check;
int x;
a ##1 !a, x = data_in ##1 !b[*0:$] ##1 b && (data_out == x);
endsequence
Shouldn't that line be with parentheses, such as:
a ##1 (!a, x = data_in) ##1 !b[*0:$] ##1 b && (data_out == x);
property data_check_p
int x;
a ##1 !a, x = data_in |=> !b[*0:$] ##1 b && (data_out == x);
endproperty
Shouldn't that line be with parentheses, such as:
a ##1 (!a, x = data_in) |=> !b[*0:$] ##1 b && (data_out == x);
...
sequence rep_v;
int x;
‘true,x = 0 ##0
(!a [* 0:$] ##1 a, x = x+data)[*4] ##1 b ##1 c && (data_out == x);
endsequence
Shouldn't that line be with parentheses, such as:
(!a [* 0:$] ##1 (a, x = x+data))[*4] ##1 b ##1 c && (data_out == x);
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* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
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* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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Received on Sun May 2 18:10:14 2004