Subject: Re: [sv-ac] Draft 5 review meeting
From: John Havlicek (john.havlicek@motorola.com)
Date: Wed Mar 03 2004 - 12:15:15 PST
Hi Adam:
> Annex H "SystemVerilog Concurrent Assertion Semantics"
>
> Recommend renaming to "Formal assertion semantics" ?
> "The word SystemVerilog is not necessary.
> It also discusses procedural and concurrent semantics.
> Having the word formal keys the reader to a methematical base.
> Would have to update the introduction section.
My understanding of the terminology in Section 17 is that the
assertions are partitioned into "immediate" and "concurrent",
so I think "concurrent" is accurate. I agree that "SystemVerilog" is
not necessary. How about
Formal Semantics of Concurrent Assertions
as the annex title?
Best regards,
John H.
> Date: Tue, 02 Mar 2004 18:00:33 -0600
> From: Adam Krolnik<krolnik@lsil.com>
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>
>
> Hi;
>
>
> Here's my comments on section by section...
>
> 17.7.11 "Implication" should be inserted before 17.12 "Multiple clock support"
> and the property operator text from 17.11 should be moved into it.
>
>
> Annex H "SystemVerilog Concurrent Assertion Semantics"
>
> Recommend renaming to "Formal assertion semantics" ?
> "The word SystemVerilog is not necessary.
> It also discusses procedural and concurrent semantics.
> Having the word formal keys the reader to a methematical base.
> Would have to update the introduction section.
>
> Should we add 'assumptions' to the introduction section?
>
>
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
> Co-author "Assertion Based Design"
>
>
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