Subject: Re: [sv-ac] Draft 5 review meeting
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Mar 02 2004 - 16:00:33 PST
Hi;
Here's my comments on section by section...
17.7.11 "Implication" should be inserted before 17.12 "Multiple clock support"
and the property operator text from 17.11 should be moved into it.
Annex H "SystemVerilog Concurrent Assertion Semantics"
Recommend renaming to "Formal assertion semantics" ?
"The word SystemVerilog is not necessary.
It also discusses procedural and concurrent semantics.
Having the word formal keys the reader to a methematical base.
Would have to update the introduction section.
Should we add 'assumptions' to the introduction section?
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-author "Assertion Based Design"
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