RE: [sv-ac] Feedback request

Hi Shalom,

In http://www.eda-twiki.org/sv-ac/hm/att-11541/1800_new_proposals_ben.pdf , regarding http://www.eda-twiki.org/svdb/view.php?id=3478 Ben writes, “This is a feature that is missing in SystemVerilog; it is very much needed for assertions and formal verification when describing out or inout ports of a sub-unit that is embedded into higher levels of hierarchy.”

In http://www.eda-twiki.org/sv-ac/hm/11533.html you pointed out that this issue “properly belongs to SV-BC”. So this enhancement shouldn’t end up on a final scope document without discussing with SV-BC.

By the way, there’s no mention of ‘tran’ in Ben’s proposal, but in your comment 16490 you write, “The described case seems to be part of a more general case, which is any net that has multiple drivers. You would like to be able to see the information about each individual driver. Since tools already implement this by a "Show Drivers" command, I don't see why it is so difficult. The advantage is being able to see the information from within the language. When I was writing testbenches, that capability would sometimes have been very useful. Another special case, almost the same as the inout port, is where two nets are connected by a bidirectional transistor primitive (tran) and you want to see what is driven from each side of the primitive.”

-- Brad


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