RE: [sv-ac] P1800 SV-AC meeting

I think #1 properly belongs to SV-BC.

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Ben Cohen
Sent: Thursday, November 06, 2014 18:57
To: Korchemny, Dmitry
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] P1800 SV-AC meeting

Dmitry and all,
I have 3 items that I particularly would like to see in the next version of 1800; those items are mostly derived from what I see from users who post questions on verification newsgroups.  These include:

1)  0003478: Make drivers of inout ports accessible
       http://www.eda-stds.org/svdb/view.php?id=3478

       Taking account for external and internal drivers on inouts is important when verifying IPs (commercial or user defined) inserted into a higher level structure.

2) concurrent assertions in classes.
I understand that e allows such a thing, perhaps someone who knows e can expand on its usage.  However, we can handle assertions in the following manner:
​     a)
assertions become active dynamically.
     b) tool will have to start collecting and reporting on concurrent assertions in a class when the class is instanced.              c) tool will have to stop collecting and freeze the reporting on concurrent assertions in a class when the classes is nulled.
     d) A reference to a null object in an assertion would make that assertion vacuous.
Below is an example of my thoughts.  I forgot if we have a mantis on this, maybe we do. I am open to any suggestions.
 interface A_if (input logic clk);
    // ..

     clocking driver_cb @ (posedge clk);
         output rst_n, data_in, ld, kind_cp;
         input A;
     endclocking : driver_cb

     modport drvr_if_mp (clocking driver_cb);
 endinterface : A_if

class A_driver extends uvm_driver #(A_xactn, A_xactn);
          string tID;
          virtual interface A_if.drvr_if_mp vif;
          rand bit[3:0] ct;
          bit a, b, c;
          function new(string name, uvm_component parent);
          //...
          endfunction : new

          `uvm_component_utils_begin(A_driver)
          `uvm_field_object(req, UVM_ALL_ON)
          `uvm_component_utils_end

          task get_and_drive();

    ap_abc: assert property(@(this.vif.driver_cb)
                      this.vif.A_cb.ld |=> a ##1 constraint <= 4'b1100);
endclass : A_driver

module forsv_ac;
    A_driver a_dvr1;
    // ...

endmodule

3) Allow module (checker, etc) variables in ranges for assertions.
This is an often requested feature.  Below is an example, and an equivalent implementation.  Note that in that example, a tool can recreate an equivalent assertion with a property declaration.

module forsv_ac;
    bit a, b, c, clk;
    int v;
    // ...

    ap_option1: assert property(@(posedge clk)  a |=> ##v b);

    ap_option2: assert property(@(posedge clk)  a |=> ##[v:v b);

    ap_variation1: assert property(@(posedge clk)  a |=> ##[1:v] b);

    property p_variation1_equivalent; // Am producing an equivalent implementation
      int local_v=0; // this is an internal local variable defined by the tool
      a |=> (local_v <= v, local_v=local_v + 1'b1)[*0:$] ##1 b;
    endproperty

    ap_variation1_equivalent: assert property(@(posedge clk) p_variation1_equivalent);

endmodule


I'll make the meeting.  We can discuss them whenever we feel it is necessary; however, I just wanted for now to document them.
Ben Cohen

On Tue, Nov 4, 2014 at 9:40 AM, Korchemny, Dmitry <dmitry.korchemny@intel.com<mailto:dmitry.korchemny@intel.com>> wrote:
Agenda:
-------
- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt

- Elaborating recommendations for the next P1800 PAR.
- Opens

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