[sv-ac] Feeding checker result into module

Hi all,

We have the following example in 17.3:

checker mutex (logic sig, event clock, output bit failure);
assert property (@clock $onehot0(sig)) failure = 1'b0; else failure = 1'b1;
endchecker : mutex
module m(wire bus, logic clk);
logic res, scan;
// ...
mutex check_bus(bus, posedge clk, res);
always @(posedge clk) scan <= res;
endmodule : m

It looks to me that this example is an overkill, and should be rewritten as:
checker mutex (logic sig, event clock, output bit failure);
assert property (@clock $onehot0(sig)) failure = 1'b0; else failure = 1'b1;
endchecker : mutex
module m(wire bus, logic clk);
logic scan;
// ...
mutex check_bus(bus, posedge clk, scan);
endmodule : m

What do you think?

Thanks,
Dmitry
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