Subject: Re: [sv-ac] Straw poll on SV-AC extension proposals
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Nov 14 2003 - 15:21:24 PST
[Y] 1 additional property directive.
[N] 2 immediate assume
An assume property (...) should be sufficient as one doesn't need
previous specific state.
[Y] 3 assume synchronization
[Y] 4 local variable extensions
[Y] 5 clock_var_assign
[Y] 6 clock variable access
[N] 7 parameter in properties
I believe properties today can do all that Joseph has asked for.
It is within the argument list of a property, not separate
as parameter values are with modules.
[Y] 8 sequence passing
[Y] 9 pass $ (infinite) through property arguments.
[Y] 10 enhance implication
[Y] 11 recursive properties
[Y] 12 boolean property connectives
[Y] 13 assertions in functions
[Y] 14 gated clock support
[Y] 16 modports importing assertions
This has still not made it to the SV-BC issues page. This should be
formally mailed to them through the reflector email system so that
it is visually transferred and verifiable!
[N] 17 event created from sequence/property for reactive functionality.
[N] 18 extend wait to work on sequence/property
These proposals only work for code in program blocks. This is not
sufficient. I would vote for a proposal that supports RTL code
access to sequences/properties.
[N] 19 embed assertions in structures.
This will only work if one defines a default clock domain in each module
used. We have not talked about this at all.
We have discussed this, but still have not found a working solution.
[Y] Proposal for action blocks using sampled variable values.
Proposal for error message having access to local variables.
Here's John's.
[Y] accessing local variables
[Y] sampling local variables
[Y] clock flow
[Y] generalized implication
[Y] property conjunction
[Y] property disjunction
[Y] property if else
[Y] property instances
[Y] property negation
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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