[sv-ac] RE: Champion comments Mantis 2476 (http://www.verilog.org/mantis/view.php?id=2476)

From: Rich, Dave <Dave_Rich@mentor.com>
Date: Fri Jul 01 2011 - 10:39:51 PDT

Erik,

The syntax for the maximum size of a queue was specifically added to address synthesis concerns. I don't know if any synthesis tool has implemented it though. IMHO, any constant expression should be synthesizable regardless of its data type.

Dave Rich
Verification Technologist
Mentor Graphics Corporation
New Office Number: 510-354-7439
[Description: Twitter-32]<http://www.twitter.com/dave_59> [Description: Technorati-32] <http://go.mentor.com/drich>

From: Seligman, Erik [mailto:erik.seligman@intel.com]
Sent: Friday, July 01, 2011 9:38 AM
To: Rich, Dave
Cc: sv-ac@eda-stds.org
Subject: Q: Champion comments Mantis 2476 (http://www.verilog.org/mantis/view.php?id=2476)

Hi Dave-In your champion comments on this Mantis, you suggested that it might be nice to take a queue like {'1, 'x} as an arg to the new $countbits function.

   The SV-BC should review the control_bits functionality in $countbits. It's
   seems very un-Verilog-like to have an argument treat 1'b1 and 2'b01
   differently. I would rather it take a queue of logic. Then you could write
   {1} or {'x,'z} as arguments, and would not need to do the repeated bits
   trick. Alternatively make the argument 4-bits and always require the
   repeated bits.

I like the idea, but one issue occurs to me: are queues generally considered part of the synthesizable subset of the language? I'm wondering since I haven't encountered them in formal/assertion contexts before. If not, would this make it inadvisable to require them in a function likely to appear in assertions?

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


image001.png
image002.png
Received on Fri Jul 1 10:40:17 2011

This archive was generated by hypermail 2.1.8 : Fri Jul 01 2011 - 10:40:21 PDT