[sv-ac] Q: Champion comments Mantis 2476 (http://www.verilog.org/mantis/view.php?id=2476)

Hi Dave-In your champion comments on this Mantis, you suggested that it might be nice to take a queue like {'1, 'x} as an arg to the new $countbits function.

   The SV-BC should review the control_bits functionality in $countbits. It's
   seems very un-Verilog-like to have an argument treat 1'b1 and 2'b01
   differently. I would rather it take a queue of logic. Then you could write
   {1} or {'x,'z} as arguments, and would not need to do the repeated bits
   trick. Alternatively make the argument 4-bits and always require the
   repeated bits.

I like the idea, but one issue occurs to me: are queues generally considered part of the synthesizable subset of the language? I'm wondering since I haven't encountered them in formal/assertion contexts before. If not, would this make it inadvisable to require them in a function likely to appear in assertions?

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